Media management based on data access metrics

ABSTRACT

A system includes: a memory device; and a processing device, operatively coupled with the memory device, to perform operations including: dividing a translation map into a plurality of portions of the translation map, the translation map mapping a plurality of logical block addresses to a plurality of physical block addresses of the memory device, each of the plurality of portions of the translation map corresponding to a plurality of blocks of the memory device, wherein a portion of the plurality of portions of the translation map comprises a plurality of entries, each entry mapping a logical block address to a physical block address of the memory device; updating, responsive to receiving a data access request, a counter of data access operations performed using each of the plurality of portions of the translation map; responsive to determining that a predefined condition is satisfied, identifying a portion of the plurality of portions of the translation map based on the counter of data access operations; identifying a block among a plurality of blocks of the memory device corresponding to the identified portion of the translation map; and performing a garbage collection operation on the identified block.

RELATED APPLICATIONS

The present application is a continuation of U.S. application Ser. No.16/943,143, filed Jul. 30, 2020, entitled “MEDIA MANAGEMENT BASED ONDATA ACCESS METRIC,” which is incorporated by reference herein.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems,and more specifically, relate to performing garbage collectionoperations based on data access metrics in memory sub-systems.

BACKGROUND

A memory sub-system can include one or more memory devices that storedata. The memory devices can be, for example, non-volatile memorydevices and volatile memory devices. In general, a host system canutilize a memory sub-system to store data at the memory devices and toretrieve data from the memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure will be understood more fully from the detaileddescription given below and from the accompanying drawings of variousembodiments of the disclosure. The drawings, however, should not betaken to limit the disclosure to the specific embodiments, but are forexplanation and understanding only.

FIG. 1 illustrates an example computing system that includes a memorysub-system in accordance with some embodiments of the presentdisclosure.

FIG. 2 depicts criteria for selection of blocks for performing garbagecollection operations, in accordance with some embodiments of thepresent disclosure.

FIG. 3 depicts an example of performing garbage collection operationsbased on data access metrics, in accordance with some embodiments of thepresent disclosure.

FIG. 4 is a flow diagram of an example method to perform garbagecollection operations based on number of data access operations, inaccordance with some embodiments of the present disclosure.

FIG. 5 is a flow diagram of an example method for migrating data basedon a data migration criterion associated with regions of a translationmap, in accordance with some embodiments of the present disclosure.

FIG. 6 is a block diagram of an example computer system in whichembodiments of the present disclosure may operate.

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to performing garbagecollection operations based on data access metrics in a memorysub-system. A memory sub-system can be a storage device, a memorymodule, or a hybrid of a storage device and memory module. Examples ofstorage devices and memory modules are described below in conjunctionwith FIG. 1 . In general, a host system can utilize a memory sub-systemthat includes one or more memory components, such as memory devices thatstore data. The host system can provide data to be stored at the memorysub-system and can request data to be retrieved from the memorysub-system.

The memory devices can include volatile and non-volatile memory devicesthat can store data from the host system. One example of non-volatilememory devices is a negative-and (NAND) memory device. Other examples ofnon-volatile memory devices are described below in conjunction with FIG.1 . Each of the non-volatile memory devices can include one or morearrays of memory cells. A memory cell (“cell”) is an electronic circuitthat stores information. Depending on the cell type, a cell can storeone or more bits of binary information, and has various logic statesthat correlate to the number of bits being stored. The logic states canbe represented by binary values, such as “0” and “1”, or combinations ofsuch values. For example, a single level cell (SLC) can store one bit ofinformation and has two logic states. As another example, a quad levelcell (QLC) can store four bits of information and has sixteen logicstates.

Various memory access operations can be performed on the memory cells.Data can be written to, read from, and erased from memory cells. Memorycells can be grouped into a write unit, such as a page. For some typesof memory devices, a page is the smallest write unit. A page sizerepresents a particular number of cells of a page. For some types ofmemory devices (e.g., NAND), memory cells can be grouped into an eraseunit, such as a physical block, which is a group of pages. A physicalblock is a 2-dimensional memory array of pages (rows of cells) andstrings (columns of cells). Data can be written to a block,page-by-page. Data can be erased at a block level. However, portions ofa block cannot be erased.

Memory cells in the same erase unit (e.g., block) can be configured tostore a specific number of bits of information. For example, a quadlevel cell (QLC) block includes memory cells configured to store fourbits of information. Accordingly, a QLC block, for example, can storemore bits of information than a single level cell (SLC) block (havingmemory cells configured to store one bit of information).

A memory sub-system controller can perform operations for mediamanagement algorithms, such as wear leveling, refresh, garbagecollection, scrub, etc., to help manage the data on the memorysub-system. A block may have some pages containing valid data and somepages containing invalid data. To avoid waiting for all of the pages inthe block to have invalid data in order to erase and reuse the block, analgorithm hereinafter referred to as “garbage collection” can be invokedto allow the block to be erased and released as a free block forsubsequent write operations. Garbage collection is a set of mediamanagement operations that include, for example, selecting a block thatcontains valid and invalid data, selecting pages in the block thatcontain valid data, copying the valid data to new locations (e.g., freepages in another block), marking the data in the previously selectedpages as invalid, and erasing the selected block.

When the host system requests to store data, the data is stored at aphysical address within the memory component. The host system provides alogical address identifying the data to be stored. A logical to physical(L2P) translation map is maintained to identify the physical locationwhere the data corresponding to each logical address resides. When thedata is written to the memory component, it can be done at the writeunit level, that is, at the page level, such that an entire page, ormultiple pages, is written in a single operation. When the host systemrequests to update data at a particular logical address, the updateddata is stored at a new physical location (e.g., a new physical address)and the L2P mapping is updated so that the particular logical address ofthe new data is mapped to the new physical address. The original data(e.g., the data prior to the update) still remains stored in theoriginal physical address. This data, however, is no longer valid fromthe host's perspective, and is no longer usable by the host. Withvarious changes in data, the memory component accumulates physicaladdresses across various physical blocks that have invalid data, inaddition to having physical addresses with valid data. The invalid datastored at the memory component is considered “garbage” and can becleaned out at some point.

When the memory component is full, such that there is insufficientcapacity to accept data from additional write operations, certain datacan be erased in order to free up space. When data is erased from thememory component, it is done at the erase unit level, that is, at thephysical block level, such that an entire block (including multiplepages) is erased in a single operation. Thus, when a particular segmentof data on the memory component is updated, certain pages in a blockwill have data that is no longer needed. A block may have some pagescontaining valid data and some pages containing invalid data, so theentire block cannot be erased due to the need for preserving the validdata. A memory sub-system controller can perform a media managementoperation for managing the space in the block. A media managementoperation, such as a garbage collection (“GC”) operation, can beperformed, which involves migrating (e.g., rewriting) those pages of theblock that contain valid data to another block, so that the currentblock with both valid and invalid data can be erased while preservingthe data at the migrated location. Garbage collection operationsinclude, for example, identifying a block that contains valid andinvalid data, selecting pages in the block that contain valid data,copying the valid data to new locations (e.g., free pages in anotherblock), marking the data in the previously selected pages as invalid,and erasing the identified block. Garbage collection is a form ofautomatic memory management that attempts to reclaim garbage, or memoryoccupied by stale data objects that are no longer in use. The basicprinciple of garbage collection is to find data objects that cannot orneed not be accessed in the future, and to reclaim the resources (i.e.storage space) used by those objects.

Since garbage collection can write the valid data to a different blockbefore the block is erased, data can be rewritten many times todifferent blocks at the memory sub-system. The amount of additionalrewrites of data in the memory sub-system is referred to herein aswrite-amplification. Write-amplification can reduce the operating lifeof a memory sub-system. To reduce write-amplification, the memorysub-system can include some amount of additional blocks in excess to atotal number of blocks that are available at any single time to storedata from the host system. Such additional blocks can be consideredover-provisioning. A larger amount of over-provisioning cansignificantly reduce write-amplification as the number of times thatdata is rewritten within the memory sub-system due to garbage collectionattempting to free up blocks is reduced.

Some of the data that the host system requests to store are written to,or overwritten in, the memory devices more frequently than others. Thefrequently-written data is referred to as “hot data” and can includejournals, file system metadata, and other frequently-updated data. Insome circumstances, a block can include data that is valid for arelatively long period of time without being overwritten. Suchinfrequently-written data is referred to as “cold data” and can includeoperating system data that rarely changes, media files, and other datathat is static or rarely updated. Thus, the hotness and the coldness ofthe data represents the level of frequency of the rewrite of data.

To select a source block on which the garbage collection operation is tobe performed, the conventional memory sub-system selects the block withthe least amount of valid data to minimize the amount of valid data thatis rewritten to a destination block. For example, the source block isselected from a pool of source blocks based on the amount of valid datain the blocks in the pool. If the pool of source blocks include anyblock that has no valid data (e.g., a valid data count for the blockequals to zero), then the block is moved from the pool of source blocksfor GC operation, as data from the block can be erased without movingany data to another location. The block with the least amount of validdata is then selected as a source block for GC operation, so that theminimum number of valid data is rewritten to a new location in order toperform the GC operation before the data in the source block can beerased. The destination block to which the valid data is rewritten istypically selected by identifying the youngest (i.e., the least recentlymodified) free block available for the rewrite of the valid data.Typically, the selection of the source and destination blocks areperformed without factoring in the hotness and/or coldness (e.g.,frequency of overwrites) of the data in the blocks, and the blocks canend up having a mix of hot data and cold data.

Even though cold data does not need to be rewritten to a differentlocation without a change in the data, unchanged cold data that islocated on the same memory block as hot data is likely to be copied tonew block numerous times by garbage collection operations because ofchanges to the hot data located on the same block. Thus, repeatedwriting of the same data that has been previously written, referred toas write amplification, is increased because of cold data and hot databeing located on the same block. “Hot blocks” that contain primarily hotdata are more likely to be selected for garbage collection because hotdata is frequently invalidated, and garbage collection algorithms selectblocks having the lowest amount of valid data for garbage collection.Any cold data that is stored in the hot blocks increases garbagecollection effort and write amplification, and is more likely to beprocessed by in garbage collection operations because it is in the sameblocks as hot data. Increased write amplification reduces theperformance of the memory sub-system. The repeated write operations canreduce response time and throughput, and also reduce the lifespan of thememory devices that store the data.

Aspects of the present disclosure addresses the above and otherdeficiencies by performing garbage collection operation based on dataaccess metrics in memory sub-systems. The memory sub-system can receivea data access request, such as a read request or a write request, fromthe host system. The host system can provide the logical blocks on whichthe data access is to be performed. The memory sub-system can use alogical to physical (L2P) translation map to identify physical blocksthat correspond to requested logical blocks. The memory sub-system canpartition the L2P map into multiple regions to keep track of data accessmetrics associated with each region of the L2P map. In an example, thepartitioned regions can be stored in a region table that can include astart L2P entry, size (e.g., length) of the region if the size isvariable, counters, etc. The memory sub-system can partition the regionsbased on various factors. The granularity and/or the number of regionsfor the partition can depend on these factors. For example, one factorbased on which the regions can be partitioned is available memory space.In an example, available memory space can refer to the available spaceon the memory location where the regions (e.g., region table) arestored. For example, the L2P map regions can be stored in a cache space,DRAM space, etc. In another example, if the memory sub-system utilizes apower down capacitor, the memory sub-system can partition the regionsbased on the budget (e.g., capacity) allocated for the power downcapacitor. For example, the power down capacitor may be able to processa limited amount of data when necessary. For each region, the memorysub-system can maintain a counter to track the number of data accessoperations requested by the host system that are associated with logicalblocks in the region. For example, each time a write request is directedto a logical block that belongs to a specific region of the L2P map, awrite counter can be increased for the specific region. The counters canbe used as the data access metrics. The memory sub-system can maintain aheat map based on the counters, where a first region is considered to behotter than a second region if the counter value associated with thefirst region is higher than the counter value associated with the secondregion. When GC is triggered, the memory subsystem can select a block toperform the GC using the heat map. The memory sub-system can select aregion that meets the criteria for being a cold region. For example, thememory sub-system can select the region with the minimum counter valueamong all L2p map regions. The memory sub-system can then select asource block from the set of blocks associated with the selected coldregion (e.g., the block that has the least amount of valid data). Indoing so, the memory sub-system can still achieve the goal of doingminimum work during GC by selecting a block with low amount of validdata, while avoiding to select hot data that belongs to a hot regionwhen performing GC, which would then get invalidated by host soon andincrease write amplification.

Advantages of the present disclosure include, but are not limited to,decreasing write amplification, decreasing power consumption, increasingendurance of the memory device, requiring less resources andcomputational power, and/or freeing system resources for otherfunctionalities. Since the data access metrics, such as frequency ofoverwrites of data, are factored into the selection of blocks for mediamanagement operations, such as garbage collection, the mixing offrequently overwritten data to infrequently overwritten data can beavoided while performing the garbage collection operations. By selectinginfrequently overwritten data for GC, the memory device can also avoidunnecessarily rewriting frequently overwritten data to another locationwhich is likely to be invalidated again soon. These improvements lead toreducing write amplification. The reduced write amplification canprovide for improved performance of the memory sub-system as fewer writeoperations are performed as part of the garbage collection operation,and increased storage efficiency. The reduction in the number of writesto blocks of physical memory can also increase the endurance andoperating lifespan of the memory sub-system, since fewer writeoperations are performed as part of the garbage collection operations.

FIG. 1 illustrates an example computing system 100 that includes amemory sub-system 110 in accordance with some embodiments of the presentdisclosure. The memory sub-system 110 can include media, such as one ormore volatile memory devices (e.g., memory device 140), one or morenon-volatile memory devices (e.g., memory device 130), or a combinationof such.

A memory sub-system 110 can be a storage device, a memory module, or ahybrid of a storage device and memory module. Examples of a storagedevice include a solid-state drive (SSD), a flash drive, a universalserial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC)drive, a Universal Flash Storage (UFS) drive, a secure digital (SD)card, and a hard disk drive (HDD). Examples of memory modules include adual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), andvarious types of non-volatile dual in-line memory module (NVDIMM).

The computing system 100 can be a computing device such as a desktopcomputer, laptop computer, network server, mobile device, a vehicle(e.g., airplane, drone, train, automobile, or other conveyance),Internet of Things (IoT) enabled device, embedded computer (e.g., oneincluded in a vehicle, industrial equipment, or a networked commercialdevice), or such computing device that includes memory and a processingdevice.

The computing system 100 can include a host system 120 that is coupledto one or more memory sub-systems 110. In some embodiments, the hostsystem 120 is coupled to different types of memory sub-system 110. FIG.1 illustrates one example of a host system 120 coupled to one memorysub-system 110. As used herein, “coupled to” or “coupled with” generallyrefers to a connection between components, which can be an indirectcommunicative connection or direct communicative connection (e.g.,without intervening components), whether wired or wireless, includingconnections such as electrical, optical, magnetic, etc.

The host system 120 can include a processor chipset and a software stackexecuted by the processor chipset. The processor chipset can include oneor more cores, one or more caches, a memory controller (e.g., NVDIMMcontroller), and a storage protocol controller (e.g., PCIe controller,SATA controller). The host system 120 uses the memory sub-system 110,for example, to write data to the memory sub-system 110 and read datafrom the memory sub-system 110.

The host system 120 can be a computing device such as a desktopcomputer, laptop computer, network server, mobile device, or suchcomputing device that includes a memory and a processing device. Thehost system 120 can be coupled to the memory sub-system 110 via aphysical host interface. Examples of a physical host interface include,but are not limited to, a serial advanced technology attachment (SATA)interface, a peripheral component interconnect express (PCIe) interface,universal serial bus (USB) interface, Fibre Channel, Serial AttachedSCSI (SAS), a double data rate (DDR) memory bus, Small Computer SystemInterface (SCSI), a dual in-line memory module (DIMM) interface (e.g.,DIMM socket interface that supports Double Data Rate (DDR)), Open NANDFlash Interface (ONFI), Double Data Rate (DDR), Low Power Double DataRate (LPDDR), or any other interface. The physical host interface can beused to transmit data between the host system 120 and the memorysub-system 110. The host system 120 can further utilize an NVM Express(NVMe) interface to access components (e.g., memory devices 130) whenthe memory sub-system 110 is coupled with the host system 120 by thePCIe interface. The physical host interface can provide an interface forpassing control, address, data, and other signals between the memorysub-system 110 and the host system 120. FIG. 1 illustrates a memorysub-system 110 as an example. In general, the host system 120 can accessmultiple memory sub-systems via a same communication connection,multiple separate communication connections, and/or a combination ofcommunication connections.

The memory devices 130,140 can include any combination of the differenttypes of non-volatile memory devices and/or volatile memory devices. Thevolatile memory devices (e.g., memory device 140) can be, but are notlimited to, random access memory (RAM), such as dynamic random accessmemory (DRAM) and synchronous dynamic random access memory (SDRAM).

Some examples of non-volatile memory devices (e.g., memory device 130)include negative-and (NAND) type flash memory and write-in-place memory,such as three-dimensional cross-point (“3D cross-point”) memory, whichis a cross-point array of non-volatile memory cells. A cross-point arrayof non-volatile memory can perform bit storage based on a change of bulkresistance, in conjunction with a stackable cross-gridded data accessarray. Additionally, in contrast to many flash-based memories,cross-point non-volatile memory can perform a write in-place operation,where a non-volatile memory cell can be programmed without thenon-volatile memory cell being previously erased. NAND type flash memoryincludes, for example, two-dimensional NAND (2D NAND) andthree-dimensional NAND (3D NAND).

Each of the memory devices 130 can include one or more arrays of memorycells. One type of memory cell, for example, single level cells (SLC)can store one bit per cell. Other types of memory cells, such asmulti-level cells (MLCs), triple level cells (TLCs), quad-level cells(QLCs), and penta-level cells (PLCs) can store multiple bits per cell.In some embodiments, each of the memory devices 130 can include one ormore arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, or anycombination of such. In some embodiments, a particular memory device caninclude an SLC portion, and an MLC portion, a TLC portion, a QLCportion, or a PLC portion of memory cells. The memory cells of thememory devices 130 can be grouped as pages that can refer to a logicalunit of the memory device used to store data. With some types of memory(e.g., NAND), pages can be grouped to form blocks. Some types of memory,such as 3D cross-point, can group pages across dice and channels.

Although non-volatile memory components such as 3D cross-point array ofnon-volatile memory cells and NAND type flash memory (e.g., 2D NAND, 3DNAND) are described, the memory device 130 can be based on any othertype of non-volatile memory, such as read-only memory (ROM), phasechange memory (PCM), self-selecting memory, other chalcogenide basedmemories, ferroelectric transistor random-access memory (FeTRAM),ferroelectric random access memory (FeRAM), magneto random access memory(MRAM), Spin Transfer Torque (STT)-MRAM, conductive bridging RAM(CBRAM), resistive random access memory (RRAM), oxide based RRAM(OxRAM), negative-or (NOR) flash memory, and electrically erasableprogrammable read-only memory (EEPROM).

A memory sub-system controller 115 (or controller 115 for simplicity)can communicate with the memory devices 130 to perform operations suchas reading data, writing data, or erasing data at the memory devices 130and other such operations. The memory sub-system controller 115 caninclude hardware such as one or more integrated circuits and/or discretecomponents, a buffer memory, or a combination thereof. The hardware caninclude a digital circuitry with dedicated (i.e., hard-coded) logic toperform the operations described herein. The memory sub-systemcontroller 115 can be a microcontroller, special purpose logic circuitry(e.g., a field programmable gate array (FPGA), an application specificintegrated circuit (ASIC), etc.), or other suitable processor.

The memory sub-system controller 115 can be a processing device, whichincludes one or more processors (e.g., processor 117), configured toexecute instructions stored in a local memory 119. In the illustratedexample, the local memory 119 of the memory sub-system controller 115includes an embedded memory configured to store instructions forperforming various processes, operations, logic flows, and routines thatcontrol operation of the memory sub-system 110, including handlingcommunications between the memory sub-system 110 and the host system120.

In some embodiments, the local memory 119 can include memory registersstoring memory pointers, fetched data, etc. The local memory 119 canalso include read-only memory (ROM) for storing micro-code. While theexample memory sub-system 110 in FIG. 1 has been illustrated asincluding the memory sub-system controller 115, in another embodiment ofthe present disclosure, a memory sub-system 110 does not include amemory sub-system controller 115, and can instead rely upon externalcontrol (e.g., provided by an external host, or by a processor orcontroller separate from the memory sub-system).

In general, the memory sub-system controller 115 can receive commands oroperations from the host system 120 and can convert the commands oroperations into instructions or appropriate commands to achieve thedesired access to the memory devices 130 and/or the memory device 140.The memory sub-system controller 115 can be responsible for otheroperations such as wear leveling operations, garbage collectionoperations, error detection and error-correcting code (ECC) operations,encryption operations, caching operations, and address translationsbetween a logical address (e.g., logical block address (LBA), namespace)and a physical address (e.g., physical block address) that areassociated with the memory devices 130. The memory sub-system controller115 can further include host interface circuitry to communicate with thehost system 120 via the physical host interface. The host interfacecircuitry can convert the commands received from the host system intocommand instructions to access the memory devices 130 and/or the memorydevice 140 as well as convert responses associated with the memorydevices 130 and/or the memory device 140 into information for the hostsystem 120.

The memory sub-system 110 can also include additional circuitry orcomponents that are not illustrated. In some embodiments, the memorysub-system 110 can include a cache or buffer (e.g., DRAM) and addresscircuitry (e.g., a row decoder and a column decoder) that can receive anaddress from the memory sub-system controller 115 and decode the addressto access the memory devices 130.

In some embodiments, the memory devices 130 include local mediacontrollers 135 that operate in conjunction with memory sub-systemcontroller 115 to execute operations on one or more memory cells of thememory devices 130. An external controller (e.g., memory sub-systemcontroller 115) can externally manage the memory device 130 (e.g.,perform media management operations on the memory device 130). In someembodiments, a memory device 130 is a managed memory device, which is araw memory device combined with a local controller (e.g., localcontroller 135) for media management within the same memory devicepackage. An example of a managed memory device is a managed NAND (MNAND)device.

The memory sub-system 110 includes a heat map component 113 that can beused to maintain data access metrics for use with a garbage collectionoperation on the blocks of memory device 130 and 140. In someembodiments, the memory sub-system controller 115 includes at least aportion of the heat map component 113. For example, the memorysub-system controller 115 can include a processor 117 (processingdevice) configured to execute instructions stored in local memory 119for performing the operations described herein. In some embodiments, theheat map component 113 is part of the host system 110, an application,or an operating system.

In one embodiment, the heat map component 113 can use the logical tophysical (L2P) translation map, which maps logical block addresses tophysical block addresses, to derive a heat map for the memory device 130and/or 140. The heat map component 113 can divide the L2P map intomultiple regions. The heat map component 113 can track a number of dataaccess operations associated with each region of the L2P map. The heatmap component 113 can track the number of data access operations usingone or more counters associated with each region of the L2P map. Forexample, when the host system 120 sends a write request to store dataspecifying a logical block, heat map component 113 can increase a writecounter to track the number of write operations performed using theregion associated with the specified logical block in the write request.In another example, when the host system 120 sends a read request toread data from the memory device 130 and/or 140, the heat map component113 can increase a read counter to track the number of read operationsperformed using the region associated with the specified logical blockin the read request. The counters can be used as the data accessmetrics. The heat map component 113 can derive a heat map of the logicalspace of the memory device based on the counters. The value of thecounter associated with a region can be proportionate to the hotness ofthe region as a whole. That is, the higher the counter value, the hotterthe region. The heat map component 113 can designate a first L2P regionto be hotter than a second L2P region if the counter value associatedwith the first L2P region is higher than the counter value associatedwith the second L2P region. In some implementations, the heat mapcomponent 113 can select a source block for performing the GC operationusing the heat map. The heat map component 113 can select an L2P regionthat meets the criteria for being a cold region. For example, the heatmap component 113 can select the region with the least counter value. Inanother example, the heat map component 113 can select a region that hasa counter value that is below a threshold metric. The heat map component113 can then select a block from the set of blocks associated with theselected region, based on the amount of valid data. For example, theblock with the least amount of valid data can be selected as the sourceblock for the GC operation. When the GC operation is triggered, the heatmap component 113 can provide the source block for performing the GCoperation. In another implementation, the memory sub-system, or acomponent of the memory sub-system, can select the source block forperforming the GC operation using the heat map generated by the heat mapcomponent 113. Further details with regards to the operations of theheat map component 113 are described below.

FIG. 2 depicts criteria for selection of blocks for performing garbagecollection operations in a memory sub-system 200, in accordance withsome embodiments of the present disclosure. Memory sub-system 200 caninclude a controller that determines when it is appropriate to initiatea media management operation. In an example, the media managementoperation can include a garbage collection operation. When thecontroller determines that a criterion to perform a garbage collectionoperation is satisfied, the controller can initiate the garbagecollection operation, as depicted in block 201. A GC operation that canbe invoked in the background without disrupting host requests is knownas a background GC (“BGC”) operation. For example, GC can be initiatedperiodically as part of regular memory management operations for thememory sub-system. In some examples, the controller can determine thatthe memory sub-system, or certain components within the memorysub-system, is in an idle state or is experiencing downtime and a BGCcan be performed during this time. In an example, during host idle time,a BGC operation can be performed to relocate host data stored in astatic single level cell (SLC) cache to reclaim the blocks. On the otherhand, a GC operation that takes place concurrently with host requests oris prioritized before the host requests is known as foreground or activeGC (“AGC”). In some examples, GC is initiated in response to aparticular event, such as, receiving a particular write request (e.g.,from the host system) and a determination that memory components haveinsufficient capacity to accept the write request. In some examples, thecontroller can determine that the memory component is full and/or thereis insufficient capacity to accept any additional potential writeoperations that can be received from the host and that garbagecollection needs to be performed to free up space in the memorycomponent. In some example, an AGC is performed to ensure data integrityis maintained. Based on the determination of the appropriate time, thecontroller can initiate the garbage collection operation to eraseinvalid data from certain blocks.

The controller can determine to initiate GC due to variouscircumstances. In some examples, performing GC can be critical due tothe particular circumstance. In other examples, performing GC can benon-critical. In some examples, performing GC can take a significantamount of time. For example, the blocks can be very fragmented due bothvalid and invalid data in various locations of each block, making the GCoperation to take a significant amount of time. In some examples,performing the GC operation can be necessary within a short amount oftime. For example, the memory component can be full and capacity toaccept additional host write requests can be insufficient, calling forthe GC operation to be performed immediately. Based on the length oftime to perform GC and how soon GC needs to be performed, thecriticality level of performing GC may vary.

The criteria for selection of source blocks for performing GC operationscan vary based on the circumstances leading to the initiation of the GCoperation. If a GC operation is initiated as depicted in block 201, thememory sub-system can determine whether the GC operation is initiateddue to ensuring data integrity, as depicted in decision point 210. Aparticular block can be prioritized for garbage collection due to thedata state metric (e.g., a bit error rate) of the block satisfying athreshold condition. The mitigation in such scenario can be to perform aGC operation. The particular block in this instance is referred to asthe “victim block.” The memory sub-system can identify the victim blockand place it in a queue to be selected as a source block for a GCoperation. The memory sub-system can maintain a pool of victim blocks.In some examples, the victim blocks can be selected for GC in the orderthe blocks were placed in the pool, such as a “first in, first out”(FIFO) order. Examples of priority victim blocks can include blocksselected due to error handling (EH), read disturb (RD), data retention(DR), background scan (BG), asynchronous power loss (APL), etc. Asdepicted in block 212, the memory sub-system can select the source blockfor the GC operation in such circumstances to be the victim block whichwas already identified as a candidate source. The destination blockwhere the data is rewritten as a result of GC can be a block that isconsidered to be a healthy block. For example, a block with a low erasecount is considered to be healthy. An erase count is the number of timesan erase operation that erases data from a data unit is performed on thedata unit during the lifetime of the data unit. The destination blockcan be selected based on the erase count associated with candidatedestination blocks. For example, a pool of candidate destination blockscan be sorted by ascending erase count associated with the blocks andthe block with the lowest erase count can be selected as the destinationblock for the GC operation.

The memory sub-system can further determine whether the GC operationshould be performed due to shortage of free blocks, as depicted indecision point 220. The memory sub-system can determine that there isnot a sufficient number of free blocks in the system per thespecification of the memory sub-system. The memory sub-system canperform GC to migrate valid data from a source block to a destinationblock and erase invalid data from the source block to free up space.

In the memory sub-system 200 of the present disclosure, the source blockfor performing the GC operation is selected in view of data accessmetrics associated with frequency of overwrite of data. The memorysub-system 200 can use a logical to physical (L2P) translation map toidentify physical blocks that correspond to requested logical blocks.The memory sub-system can partition the L2P map in multiple regions tokeep track of data access metrics associated with each region of the L2Pmap. The memory sub-system can maintain a heat map indicating the datahotness (i.e., update frequency) of a region based on counters trackingthe number of data access (e.g., write requests, read requests, etc.)directed to a region of the L2P map. A higher value for a counterindicates that a region has a higher number of hot data than anotherregion that has a lower value for the counter. When GC is triggered, thememory subsystem can select a block to perform the GC using the heatmap. The memory sub-system 200 can select a region of the L2P map thatmeets the criteria for being a cold region, such as a region with acounter value below a threshold counter value. The memory sub-system 200can then select a source block from the set of blocks associated withthe selected region based on the amount of valid data, such as a blockwith an amount of valid data below a threshold amount of valid data. Thedestination block is selected based on the erase count, as describedwith respect to block 212. The selection criteria is depicted in block222. Further details with regards to selection of the blocks for the GCoperation are described with respect to FIG. 2 .

The memory sub-system can further determine whether the GC operationshould be initiated due to static wear leveling, as depicted in decisionpoint 220. The memory components used by the memory sub-system can haveparticular properties that provide challenges in the operation of thememory sub-system. For example, some memory components, such asnon-volatile memory components, have limited endurance. For example,some memory components can be written, read, or erased a finite numberof times before physical wear causes the memory components to fail.Because of the limited endurance of memory components, techniques havebeen developed to manage wear on memory components. One technique ofmanaging the endurance of memory components is wear leveling. A wearleveling operation can attempt to evenly distribute the physical wearacross the data units (e.g., blocks) of memory components. Data of adata unit having a maximum read or write count can be swapped with dataof a data unit having a minimum read or write count in an attempt toevenly distribute the wear across the data units of memory components.Static wear leveling is a process of collecting and performing GC onlong resident data (e.g., cold data) into blocks that have higher wearthan others in the system. As such, if the GC operation is due to staticwear leveling, the memory sub-system can select as the source block thecoldest block from a pool of source blocks. In one example, the coldestblock can be identified based on the write count and/or the read countassociated with a block of the pool of source blocks. In anotherexample, the coldest region can be identified and the block with theleast amount of valid data can be selected as the source block. Thedestination block is selected based on the erase count, as describedwith respect to block 212.

FIG. 3 depicts an example of performing garbage collection operationsbased on data access metrics in a memory device 300, in accordance withsome embodiments of the present disclosure. Memory device 300 cancorrespond to the memory device 130 and/or 140 in depicted in FIG. 1 .

In one embodiment, memory device 300 is shown to include 4 channelsCHO-CH3 under physical space 301. Each channel includes two dices, witha total of eight dices D1-D8 within the physical space 301. An examplephysical block PB9 is shown to be included in die D8.

In one embodiment, a logical address space 302 can be used by the hostsystem 120 to access the memory device 300. The logical address spacecan identify a group of logical blocks (e.g., smallest host transferunit) using logical block addresses (LBAs). The host system 120 can senda data access request, such as a read request or a write request, to thememory device 300 directed to the logical address space 302. The hostsystem 120 can provide logical block addresses on which the data accessis to be performed.

The memory device 300 can maintain a logical to physical (L2P)translation map 310. In an example, the L2P map 310 can map logicalblocks 320 to physical blocks 330, where a logical block LB6 is shown tocorrespond to a physical block PB6. In one example, the L2P map 310 canmap logical block addresses to physical block addresses. In anotherexample, the L2P map can describe the relationship between the logicalblocks and the physical blocks using other groupings of the logical andphysical blocks. For example, a translation unit (TU) can be used toidentify the smallest portion of an L2P map. A TU can comprise a groupof LBAs. A TU can be mapped to groups of pages, physical blocks, etc.The memory device 300 can use the L2P map 310 to identify physicalblocks that correspond to requested logical blocks to perform the dataaccess requests of the host system 120.

In an embodiment of the present disclosure, heat map component 113 canuse the L2P map 310 to derive a heat map 340 for the memory device 300.The heat map component 113 can divide the L2P map 310 into multipleportions. In the example of FIG. 2 , the L2P map 310 is divided in “n”regions (e.g., portions), from region R1 to region Rn to derive the heatmap 340. Although heat map 340 is shown as a separate element in theexample, heat map 340 can be part of the L2P map 310 in other examples.The heat map component 113 can track a metric associated with eachregion of the L2P map. For example, the heat map component 113 can trackmetric m1 associated with region R1, and so on. Heat map 340 canidentify metrics m1-mn corresponding to regions R1-Rn. Heat map 340 caninclude objects, metadata, tags, etc. to identify which portion of theL2P map 310 is included in each region of R1-Rn. In an example, themetrics can identify frequency of data access associated with eachregion of the translation map. For example, the metrics can identifywhich region has more hot data than other regions.

In an embodiment, a metric in the heat map 340 can comprise a number ofdata access operations associated with a particular region of the L2Pmap 310. The heat map component 113 can track the number of data accessoperations using one or more counters associated with each region of theL2P map. The counters can include a read counter, a write counter, or acombination thereof. For example, whenever the host system 120 sends awrite request to store data by specifying a particular logical block,heat map component 113 can increase a write counter associated with aregion corresponding to the particular logical block. The write counterthus tracks the number (e.g., count) of write operations performed usingthe region associated with the particular logical block in the writerequest. For example, metric m2 can represent a write counter associatedwith region R2. When the host system 120 sends a write request directedto a logical block LB8 that corresponds to region R2, the metric m2(e.g., the write counter) associated with region R2 can be increased byone unit. In one example, the memory device 300 receives the writerequest directed to LB7 associated with region R2 of the translation map310 from host system 120, the memory device performs the write operationusing a physical block PB9 of die D8 of the memory device, updates thetranslation map to map the logical block LB7 to the physical block PB9on the region R2 of the translation map 310, and upon updating thetranslation map, updates (e.g., increases) the write counter (e.g., m2)of write operations performed using the region R2 of the translation map310. Similarly, each of the metrics m1-mn can represent a write counterassociated with each of the respective regions of the L2P map.

In another example, when the host system 120 sends a read request toread data from the memory device 300, the heat map component 113 canincrease a read counter to track the number of read operations performedusing the region associated with the specified logical block in the readrequest. In an example, each of the metrics m1-mn can represent a readcounter associated with each of the respective regions of the L2P map.In one example, the memory device 300 receives a read request directedto logical block LB9 associated with region R2 of the translation map310, performs the read operation using physical block PB2 of the memorydevice corresponding to the logical block LB9 in the L2P map 310, andupon performing the read operation, updates (e.g., increases) a readcounter (e.g., m2) of read operations performed using the region R2 ofthe translation map.

In some examples, metric m1-mn can include a separate read counter and aseparate write counter associated with each of the respective regions ofthe L2P map. In yet other examples, the metrics can represent a combinedread and write counter for tracking a number of read and write requestsdirected to each region in total.

The heat map component 113 can derive the heat map 340 of the logicalspace of the memory device using the counters that represents themetrics. The heat map 340 can indicate the hotness of data in theaggregate for each of the regions of the translation map. The value ofthe counter associated with a region can be proportionate to the hotnessof the region as a whole. That is, the higher the counter value, thehotter the region. The heat map component 113 can designate a first L2Pregion to be hotter than a second L2P region if the counter valueassociated with the first L2P region is higher than the counter valueassociated with the second L2P region. In an example, the value of thecounter m1 corresponding to region R1 is 100, the value of the counterm2 corresponding to region R2 is 50, and the value of the counter m3corresponding to region R3 is 500. The heat map thus indicates that outof the three regions R1-R3, region R3 is the hottest region because ofthe highest counter value of 500, region R1 is the second hottest regionwith the next highest counter value of 100, and the region R3 is theleast hot region with the least counter value of 50.

In some implementations, the heat map component 113 can identify asource block for performing the GC operation using the heat map. Theheat map component 113 can determine that a metric in the heat map thatis associated with a particular L2P region satisfies a data migrationcriterion for performing a GC operation. In some examples, the metricsatisfies the data migration criterion when the value of the metric isbelow a threshold value. For example, the value of the metric can bebelow a threshold T number of data access operations defined for memorydevice 300 when the criterion is considered satisfied. For example, thedata migration criterion can include migrating valid data as part of theGC operation when the data is not considered to be hot data. Moreparticularly, the data migration criterion can be defined as an L2Pregion having a metric value that is less than threshold T. In anexample, T can be equal to 120. For that example, the metric m1 and m2associated with regions R1 and R2, respectively, satisfy the datamigration criterion, as the values of m1 (100) and m2 (50) are both lessthan the threshold value of 120. In that case, both regions R1 and R2can be selected for further consideration for selecting, as a sourceblock, a particular physical block associated with the regions R1 andR2. The particular block selected can be selected based on amount ofvalid data in the block (e.g., the block having the least amount ofvalid data). In other examples, the data migration criterion canindicate that the value of the metric is more than or equal to athreshold value, or that the value of the metric is the highest orlowest value out of all regions, etc.

In one implementation, the heat map component 113 can identify thesource block for performing the GC operation based on the number of dataaccess operations associated with each of the regions of the L2P map310. In an example, the heat map component 113 can select an L2P regionthat meets the criteria for being a cold region. In some examples, theheat map component 113 can identify the source block for performing theGC operation by comparing the number of data access operations for eachregion of the L2P map. In some examples, the heat map component 113 canidentify the source block corresponding to a particular region ofregions R1-Rn of the L2P map where the number of data access operationsassociated with the region R2, which is 50, is less than the number ofdata access operations associated with other regions R1 and R3, whichare 100 and 500, respectively, of the L2P map. That is, the heat mapcomponent 113 can select the region with the least counter value. Inanother example, the heat map component 113 can select a region that hasa counter value that is below a threshold counter value.

Once the region is selected based on the data access metric, the heatmap component 113 can then select a particular block from the set ofblocks associated with the selected region, based on the amount of validdata. For example, the block with the least amount of valid data can beselected as the source block for the GC operation. In some examples, theamount of valid data can be tracked using a valid translation unit count(VTC). In an example, once the heat map component 113 identifies thecoldest region to be R2, the heat map component 113 can search thoughphysical blocks corresponding to logical blocks in region R2 to find thephysical block that has the least amount of valid data. In one example,out of the four physical blocks shown in column 330 in region R2,physical block PB5 can have no valid data altogether, in which case theblock is not considered for GC. The data in the block PB5 can rather beerased without migrating any data to another block since there is novalid data in that block. In another example, physical block PB9 cancontain only one page PG12 that has valid data and the remaining pageswith invalid data, while the remaining blocks PB4 and PB2 can containmore than one page of valid data. In that case, PB9 can be considered tobe the best block to select for GC, as only data from one page of theblock is to be migrated with the GC operation before erasing the data inthe block, compared to having to migrate data from multiple pages forthe other two blocks.

In an embodiment, the memory device 300 can determine that a criterionto perform a garbage collection operation is satisfied (e.g., to free upspace). In an example, when the GC operation is triggered, the heat mapcomponent 113 can provide the identified source block to memory device300 for performing the GC operation. In another example, the heat mapcomponent 113 can provide the source block to a pool of source blocksfor GC operation and when the GC operation is triggered, the memorydevice 300 can select the source block from the pool of source blocksprovided by the heat map component 113. In other embodiments, the memorydevice 300, or a component of the memory device 300, can select thesource block for performing the GC operation using the heat map 340generated by the heat map component 113.

In an embodiment, the memory device 300 performs the garbage collectionoperation on the identified block. For example, memory device 300 canperform the GC operation on identified source block PB9. In someexamples, the memory device 300 migrates data from the identified blockPB9 to another block to perform the garbage collection operation. Forexample, the memory device 300 can select pages in the block thatcontain valid data (e.g., PG12), copy the valid data from the selectedpage, write the data to a new physical block (e.g., a block with lowerase count, as described with respect to FIG. 2 ), mark the data in theselected page PG12 as invalid, and erase the identified block PB9.Thereby, the memory device 300 can complete performing the GC operationin view of the heat map 340 generated based on the tracked data accessmetrics.

FIG. 4 is a flow diagram of an example method 400 to perform garbagecollection operations based on number of data access operationsassociated with portions of a translation map, in accordance with someembodiments of the present disclosure. The method 400 can be performedby processing logic that can include hardware (e.g., processing device,circuitry, dedicated logic, programmable logic, microcode, hardware of adevice, integrated circuit, etc.), software (e.g., instructions run orexecuted on a processing device), or a combination thereof. In someembodiments, the method 400 is performed by the heat map component 113of FIG. 1 . Although shown in a particular sequence or order, unlessotherwise specified, the order of the processes can be modified. Thus,the illustrated embodiments should be understood only as examples, andthe illustrated processes can be performed in a different order, andsome processes can be performed in parallel. Additionally, one or moreprocesses can be omitted in various embodiments. Thus, not all processesare required in every embodiment. Other process flows are possible.

At operation 410, the processing logic tracks a number of data accessoperations associated with each of a plurality of portions of atranslation map. The translation map maps a plurality of logical blockaddresses to a plurality of physical block addresses of the memorydevice. In one implementation, the processing logic maintains a writecounter to track a count of write operations performed using eachportion of the plurality of portions of the translation map. In someexamples, the processing logic receives a write request directed to afirst logical block address associated with a first respective portionof the translation map, performs the write operation using a firstphysical block address of the memory device, updates the translation mapto map the first logical block address to the first physical blockaddress on the first respective portion of the translation map, and uponupdating the translation map, updates a write counter of writeoperations performed using the first respective portion of thetranslation map. In one implementation, the processing logic maintains aread counter to track a count of read operations performed using eachportion of the plurality of portions of the translation map. In someexamples, the processing logic receives a read request directed to asecond logical block address associated with a second respective portionof the translation map, performs the read operation using a secondphysical block address of the memory device corresponding to the secondlogical block address, and upon performing the read operation, updates aread counter of read operations performed using the second respectiveportion of the translation map.

At operation 420, the processing logic determines that a criterion toperform a garbage collection operation is satisfied. The garbagecollection operation is to be performed on a block of a memorycomponent. In some examples, the criterion to perform the garbagecollection operation is satisfied when a number of available blocks toperform write operations is below a threshold number.

At operation 430, the processing logic identifies the block forperforming the garbage collection operation based on the number of dataaccess operations associated with each of the plurality of portions ofthe translation map. In some examples, the processing logic identifiesthe block for performing the garbage collection operation based oncomparing the number of data access operations for each of the portionof the plurality of portions of the translation map. In some examples,the identified block is associated with a particular portion of theplurality of portions of the translation map. In some examples, theprocessing logic identifies the block corresponding to a particularportion of the plurality of portions of the translation map where thenumber of data access operations associated with the particular portionis less than the number of data access operations associated with otherportions of the plurality of portions of the translation map.

At operation 440, the processing logic performs the garbage collectionoperation on the identified block. In some examples, the processinglogic migrates data from the identified block to another block toperform the garbage collection operation.

FIG. 5 is a flow diagram of an example method 500 for migrating databased on a data migration criterion associated with regions of atranslation map, in accordance with some embodiments of the presentdisclosure. The method 500 can be performed by processing logic that caninclude hardware (e.g., processing device, circuitry, dedicated logic,programmable logic, microcode, hardware of a device, integrated circuit,etc.), software (e.g., instructions run or executed on a processingdevice), or a combination thereof. In some embodiments, the method 500is performed by the heat map component 113 of FIG. 1 . Although shown ina particular sequence or order, unless otherwise specified, the order ofthe processes can be modified. Thus, the illustrated embodiments shouldbe understood only as examples, and the illustrated processes can beperformed in a different order, and some processes can be performed inparallel. Additionally, one or more processes can be omitted in variousembodiments. Thus, not all processes are required in every embodiment.Other process flows are possible.

At operation 510, the processing logic divides a translation table intomultiple regions. The translation table maps logical block addresses tophysical block addresses of a memory device. At operation 520, theprocessing logic determines that a metric associated with a particularregion satisfies a data migration criterion. In some examples, themetric comprises a number of data access operations associated with theparticular region of the translation map. In some examples, the metricsatisfies the data migration criterion when the metric is below athreshold number of data access operations. At operation 530, theprocessing logic migrates data stored on a first block associated withthe particular region to a second block. In some examples, the firstblock has less amount of valid data compared to other blocks associatedwith the particular region.

FIG. 6 illustrates an example machine of a computer system 600 withinwhich a set of instructions, for causing the machine to perform any oneor more of the methodologies discussed herein, can be executed. In someembodiments, the computer system 600 can correspond to a host system(e.g., the host system 120 of FIG. 1 ) that includes, is coupled to, orutilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1) or can be used to perform the operations of a controller (e.g., toexecute an operating system to perform operations corresponding to theheat map component 113 of FIG. 1 ). In alternative embodiments, themachine can be connected (e.g., networked) to other machines in a LAN,an intranet, an extranet, and/or the Internet. The machine can operatein the capacity of a server or a client machine in client-server networkenvironment, as a peer machine in a peer-to-peer (or distributed)network environment, or as a server or a client machine in a cloudcomputing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box(STB), a Personal Digital Assistant (PDA), a cellular telephone, a webappliance, a server, a network router, a switch or bridge, or anymachine capable of executing a set of instructions (sequential orotherwise) that specify actions to be taken by that machine. Further,while a single machine is illustrated, the term “machine” shall also betaken to include any collection of machines that individually or jointlyexecute a set (or multiple sets) of instructions to perform any one ormore of the methodologies discussed herein.

The example computer system 600 includes a processing device 602, a mainmemory 604 (e.g., read-only memory (ROM), flash memory, dynamic randomaccess memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM, etc.), astatic memory 606 (e.g., flash memory, static random access memory(SRAM), etc.), and a data storage system 618, which communicate witheach other via a bus 630.

Processing device 602 represents one or more general-purpose processingdevices such as a microprocessor, a central processing unit, or thelike. More particularly, the processing device can be a complexinstruction set computing (CISC) microprocessor, reduced instruction setcomputing (RISC) microprocessor, very long instruction word (VLIW)microprocessor, or a processor implementing other instruction sets, orprocessors implementing a combination of instruction sets. Processingdevice 602 can also be one or more special-purpose processing devicessuch as an application specific integrated circuit (ASIC), a fieldprogrammable gate array (FPGA), a digital signal processor (DSP),network processor, or the like. The processing device 602 is configuredto execute instructions 626 for performing the operations and stepsdiscussed herein. The computer system 600 can further include a networkinterface device 608 to communicate over the network 620.

The data storage system 618 can include a machine-readable storagemedium 624 (also known as a computer-readable medium) on which is storedone or more sets of instructions 626 or software embodying any one ormore of the methodologies or functions described herein. Theinstructions 626 can also reside, completely or at least partially,within the main memory 604 and/or within the processing device 602during execution thereof by the computer system 600, the main memory 604and the processing device 602 also constituting machine-readable storagemedia. The machine-readable storage medium 624, data storage system 618,and/or main memory 604 can correspond to the memory sub-system 110 ofFIG. 1 .

In one embodiment, the instructions 626 include instructions toimplement functionality corresponding to a heat map component (e.g., theheat map component 113 of FIG. 1 ). While the machine-readable storagemedium 624 is shown in an example embodiment to be a single medium, theterm “machine-readable storage medium” should be taken to include asingle medium or multiple media that store the one or more sets ofinstructions. The term “machine-readable storage medium” shall also betaken to include any medium that is capable of storing or encoding a setof instructions for execution by the machine and that cause the machineto perform any one or more of the methodologies of the presentdisclosure. The term “machine-readable storage medium” shall accordinglybe taken to include, but not be limited to, solid-state memories,optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presentedin terms of algorithms and symbolic representations of operations ondata bits within a computer memory. These algorithmic descriptions andrepresentations are the ways used by those skilled in the dataprocessing arts to most effectively convey the substance of their workto others skilled in the art. An algorithm is here, and generally,conceived to be a self-consistent sequence of operations leading to adesired result. The operations are those requiring physicalmanipulations of physical quantities. Usually, though not necessarily,these quantities take the form of electrical or magnetic signals capableof being stored, combined, compared, and otherwise manipulated. It hasproven convenient at times, principally for reasons of common usage, torefer to these signals as bits, values, elements, symbols, characters,terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar termsare to be associated with the appropriate physical quantities and aremerely convenient labels applied to these quantities. The presentdisclosure can refer to the action and processes of a computer system,or similar electronic computing device, that manipulates and transformsdata represented as physical (electronic) quantities within the computersystem's registers and memories into other data similarly represented asphysical quantities within the computer system memories or registers orother such information storage systems.

The present disclosure also relates to an apparatus for performing theoperations herein. This apparatus can be specially constructed for theintended purposes, or it can include a general purpose computerselectively activated or reconfigured by a computer program stored inthe computer. Such a computer program can be stored in a computerreadable storage medium, such as, but not limited to, any type of diskincluding floppy disks, optical disks, CD-ROMs, and magnetic-opticaldisks, read-only memories (ROMs), random access memories (RAMs), EPROMs,EEPROMs, magnetic or optical cards, or any type of media suitable forstoring electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently relatedto any particular computer or other apparatus. Various general purposesystems can be used with programs in accordance with the teachingsherein, or it can prove convenient to construct a more specializedapparatus to perform the method. The structure for a variety of thesesystems will appear as set forth in the description below. In addition,the present disclosure is not described with reference to any particularprogramming language. It will be appreciated that a variety ofprogramming languages can be used to implement the teachings of thedisclosure as described herein.

The present disclosure can be provided as a computer program product, orsoftware, that can include a machine-readable medium having storedthereon instructions, which can be used to program a computer system (orother electronic devices) to perform a process according to the presentdisclosure. A machine-readable medium includes any mechanism for storinginformation in a form readable by a machine (e.g., a computer). In someembodiments, a machine-readable (e.g., computer-readable) mediumincludes a machine (e.g., a computer) readable storage medium such as aread only memory (“ROM”), random access memory (“RAM”), magnetic diskstorage media, optical storage media, flash memory components, etc.

In the foregoing specification, embodiments of the disclosure have beendescribed with reference to specific example embodiments thereof. Itwill be evident that various modifications can be made thereto withoutdeparting from the broader spirit and scope of embodiments of thedisclosure as set forth in the following claims. The specification anddrawings are, accordingly, to be regarded in an illustrative senserather than a restrictive sense.

What is claimed is:
 1. A system comprising: a memory device; and aprocessing device, operatively coupled with the memory device, toperform operations comprising: dividing a translation map into aplurality of portions of the translation map, the translation mapmapping a plurality of logical block addresses to a plurality ofphysical block addresses of the memory device, each of the plurality ofportions of the translation map corresponding to a plurality of blocksof the memory device, wherein a portion of the plurality of portions ofthe translation map comprises a plurality of entries, each entry mappinga logical block address to a physical block address of the memorydevice; updating, responsive to receiving a data access request, acounter of data access operations performed using each of the pluralityof portions of the translation map; responsive to determining that apredefined condition is satisfied, identifying, based on the counter ofdata access operations, a portion of the plurality of portions of thetranslation map; identifying a block among a plurality of blocks of thememory device, the block corresponding to the identified portion of thetranslation map; and performing a garbage collection operation on theidentified block.
 2. The system of claim 1, wherein determining that thepredefined condition is satisfied comprises determining that a datastate metric of a first block satisfies a threshold condition.
 3. Thesystem of claim 2, wherein the processing device is to performoperations further comprising: identifying the first block; placing thefirst block in a pool of candidate blocks for the garbage collectionoperation; and selecting a source block from the pool for the garbagecollection operation, wherein the identified block is the source block.4. The system of claim 3, wherein selecting the source block from thepool for the garbage collection operation comprises: selecting thesource block from the pool based on an order of the candidate blocksplaced in the pool.
 5. The system of claim 3, wherein selecting thesource block from the pool for the garbage collection operationcomprises: selecting the source block from the pool based on a priorityassociated with the candidate blocks placed in the pool.
 6. The systemof claim 1, wherein determining that the predefined condition issatisfied comprises determining that a number of available blocks toperform data access operations is below a threshold number.
 7. Thesystem of claim 1, wherein determining that the predefined condition issatisfied comprises determining that a state wear leveling is to beperformed.
 8. The system of claim 1, wherein identifying the portion ofthe plurality of portions of the translation map comprises: identifyingthe portion of the plurality of portions of the translation map based oncomparing a value of the counter of data access operations for each ofthe plurality of portions of the translation map.
 9. The system of claim1, wherein identifying the block among the plurality of blocks of thememory device comprises: identifying the block among the plurality ofblocks of the memory device based on an amount of valid data associatedwith each of the plurality of blocks of the memory device.
 10. Thesystem of claim 1, wherein a value of the counter of data accessoperations associated with the identified portion is less than the valueof the counter of data access operations associated with other portionsof the plurality of portions of the translation map.
 11. The system ofclaim 1, wherein the data access request comprises a request for a writeoperation, and the counter of data access operations comprises a writecounter counting the write operations performed using each of theplurality of portions of the translation map.
 12. The system of claim 1,wherein the data access request comprises a request for a readoperation, and the counter of data access operations comprises a readcounter counting the read operations performed using each of theplurality of portions of the translation map.
 13. The system of claim 1,wherein updating the counter of data access operations performed usingeach of the plurality of portions of the translation map comprises:receiving the data access request, wherein the data access requestspecifies a first logical block address associated with a first portionof the plurality of portions of the translation map; performing the dataaccess operation using a first physical block address, wherein the firstphysical block address corresponds to the first logical block address;and incrementing a value of the counter of data access operationsperformed using the first portion of the plurality of portions of thetranslation map.
 14. The system of claim 1, wherein performing thegarbage collection operation on the identified block comprises:mitigating data from the identified block to a destination block,wherein a count of erase operations performed on the destination blockis lower than a threshold value
 15. The system of claim 14, wherein theprocessing device is to perform operations further comprising: selectingthe destination block from a pool of candidate blocks, wherein the countof erase operations performed on the destination block is lowest in thepool.
 16. A method comprising: dividing, by a processing device, atranslation map into a plurality of portions of a translation map, thetranslation map mapping a plurality of logical block addresses to aplurality of physical block addresses of a memory device, each of theplurality of portions of the translation map corresponding to aplurality of blocks of the memory device, wherein a portion of theplurality of portions of the translation map comprises a plurality ofentries, each entry mapping a logical block address to a physical blockaddress of the memory device; updating, responsive to receiving a dataaccess request, a counter of data access operations performed using eachof the plurality of portions of the translation map; responsive todetermining that a predefined condition is satisfied, identifying, basedon the counter of data access operations, a portion of the plurality ofportions of the translation map; identifying a block among a pluralityof blocks of the memory device, the block corresponding to theidentified portion of the translation map; and performing a garbagecollection operation on the identified block.
 17. The method of claim16, wherein identifying the portion of the plurality of portions of thetranslation map comprises: identifying the portion of the plurality ofportions of the translation map based on comparing a value of thecounter of data access operations for each of the plurality of portionsof the translation map.
 18. The method of claim 16, wherein identifyingthe block among the plurality of blocks of the memory device comprises:identifying the block among the plurality of blocks of the memory devicebased on an amount of valid data associated with each of the pluralityof blocks of the memory device.
 19. The method of claim 16, wherein avalue of the counter of data access operations associated with theidentified portion is less than the value of the counter of data accessoperations associated with other portions of the plurality of portionsof the translation map.
 20. A non-transitory computer-readable storagemedium comprising instructions that, when executed by a processingdevice, cause the processing device to perform operations comprising:dividing, by a processing device, a translation map into a plurality ofportions of a translation map, the translation map mapping a pluralityof logical block addresses to a plurality of physical block addresses ofa memory device, each of the plurality of portions of the translationmap corresponding to a plurality of blocks of the memory device, whereina portion of the plurality of portions of the translation map comprisesa plurality of entries, each entry mapping a logical block address to aphysical block address of the memory device; updating, responsive toreceiving a data access request, a counter of data access operationsperformed using each of the plurality of portions of the translationmap; responsive to determining that a predefined condition is satisfied,identifying, based on the counter of data access operations, a portionof the plurality of portions of the translation map; identifying a blockamong a plurality of blocks of the memory device, the blockcorresponding to the identified portion of the translation map; andperforming a garbage collection operation on the identified block.